The present invention relates broadly to microprocessors, and in particular to an arrangement of multiple microprocessors which utilize a common memory.
Microcomputers are becoming increasingly important in a wide ranging variety of applications. As economies involved in the production of microprocessors and microcomputers continue to reduce the cost thereof, they will be utilized in more and more applications. It may often times be desirable to utilize more than one processing unit in conjunction with a single memory or a portion thereof. This may be desirable in order to divide the functions performed by a microcomputer among two or more processors in order to increase the capacity of the microcomputer system. Another advantage of a multiprocessor system is that lower cost may be achieved by enabling the implementation of a complex system with two or more relatively low cost processors as opposed to a single more complicated and consequently higher cost processor. A further advantage which may be obtained is that a system may be designed such that, in the event of failure of a single processor a second processor will assume the functions of the failed processor and thus provide a degree of redundancy not found in single processor systems. A still further advantage attendant a multiprocessor microcomputer system is that communications may be established between two or more processors through a shared memory directly accessible to any processor. A system of this type has the capacity for sharing not only data but also programming information and has the further advantage of allowing one processor to control the programming of another by modifying the instructions stored in a single memory. Many microprocessors currently in use are organized according to a bus structure for communication between the microprocessor and the other components of the microcomputer system as, for example, memory and input/output devices. A bus interconnection structure allows the ready modification of a microcomputer system by the substitution of components therein without the need for physical modification of the basic system hardware. Furthermore, the conventional approach to increased capability, involves dedicating a memory to a processor during the processor's entire cycle. While these prior art features are highly desirable, there still exists a need to perform the processor function at still greater speed. The present invention provides such microprocessor operation with a minimal hardware impact.